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Must have experience in developing verification environments from scratch.Strong proficiency in Verilog coding is required.Hands-on experience with simulators such as VCS, NCSim, and ModelSim.Knowledge of UVM/VMM verification methodologies...

UVM/OVM Verilog

Strong expertise in Verilog coding is required.Must have hands-on experience in synthesis.Experience with scan insertion is required.Familiarity with SpyGlass CDC/RDC tools is mandatory.Ability to perform micro-architecture development and...

CDC Spyglass Synthesis Verilog

To design, develop and support ESD solutions in differentiated sub-micron technologies like 40nm, 28nm and 18nm with specific requirements like different supply and pad voltages.• Complete in-depth understanding of basic necessary ESD struc...

✔ESD protection design and characterization (HBM CDM TLP VF-TLP) ✔Understanding of ESD devices clamps and failure mechanisms ✔Model-to-silicon correlation and validation ✔Pre-layout/post-layout simulations and verification ✔Layout implementation guidance for robust ESD solutions ✔Circuit optimization with power performance

We are seeking a Design Verification Engineer with deep expertise in Ethernet protocols and advanced SystemVerilog (SV) and Universal Verification Methodology (UVM) techniques.You will own the verification lifecycle of high-speed Ethernet i...

Ethernet. And strong in SV & UVM

Job Description: • Support Project and portfolio planning, intake, prioritization, and execution reviews across programs and projects.• Prepare for monthly intake reviews, quarterly portfolio reviews, and steering board meetings.• Ensure co...

Technical PMO Skills: MS Excel Automation (Python Ansible VBN APIs) Power BI Power Query)

3-8 years of experience in Memory/Custom Layout design.Memory Leafcell layout library design from scratch including  top level integration.Good knowledge on different types of memory architectures.Good knowledge in optimized layout design f...

Memory Leafcell DRC LVS

Job SummaryWe are looking for an experienced DV Engineer with strong expertise in Ethernet protocols and verification methodologies. The candidate will be responsible for verifying Ethernet-based SoCs/IPs and ensuring high-quality functiona...

SystemVerilog UVM Ethernet Protocols RGMII RMII MII IEEE 802.3 IEEE 802.1Q Ethernet Switching SoCs Ethernet VIP Development

We are looking for a skilled and motivated DFT Engineer with 5+ years of experience in VLSI design and verification. The ideal candidate should have strong expertise in Design for Testability (DFT) methodologies, scan insertion, ATPG, and d...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

We are looking for a SoC Verification Engineer responsible for verifying complex ASIC/SoC designs using SystemVerilog and UVM methodologies. The candidate will develop testbenches, create verification plans, debug RTL issues, and ensure fun...

SV UVM Debugging ARM SOC Verification

Key requirements include: • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis • Proficiency in simulation debug with timing/SDF • Experience with LBIST and Mixed Signal Radar ICs is highly desirable • Ability to d...

JTAG ATPG DRC LBIST