Senior Design Verification Engineer (Ethernet)

Job Summary

We are looking for an experienced DV Engineer with strong expertise in Ethernet protocols and verification methodologies. The candidate will be responsible for verifying Ethernet-based SoCs/IPs and ensuring high-quality functional verification coverage for complex networking designs.

Key Responsibilities

• Develop and execute verification plans for Ethernet IPs and SoCs
• Design and implement testbenches using SystemVerilog/UVM methodology
• Verify Ethernet protocols and interfaces including MAC interfaces such as RGMII, RMII, and MII
• Work on IEEE Ethernet standards including 802.3 and 802.1Q
• Develop reusable verification components, sequences, and coverage models
• Debug simulation failures and collaborate with design teams for issue resolution
• Perform protocol compliance and functional coverage analysis
• Support regression runs, debugging, and closure activities

Mandatory Skills

• 5–8 years of experience in Design Verification
• Strong knowledge of Ethernet protocols and standards
• Experience with MAC interfaces: RGMII, RMII, MII
• Hands-on experience with IEEE 802.3 and 802.1Q standards
• Prior experience working on Ethernet Switching SoCs or Ethernet VIP development
• Strong expertise in SystemVerilog and UVM
• Experience in writing testcases, assertions, and coverage models
• Good debugging and problem-solving skills

Preferred Skills

• Exposure to networking protocols and packet-based verification
• Experience with scripting languages such as Python or Perl
• Familiarity with industry-standard simulators and verification tools