Senior DFT Engineer

We are looking for a skilled and motivated DFT Engineer with 5+ years of experience in VLSI design and verification. The ideal candidate should have strong expertise in Design for Testability (DFT) methodologies, scan insertion, ATPG, and debugging, with hands-on experience in industry-standard EDA tools.

Role: DFT Engineer 

Experience: 5+ Years Key Responsibilities Develop and implement DFT architecture for complex SoC/IP designs. Perform scan insertion, scan stitching, and DFT verification. Generate and debug ATPG patterns for stuck-at, transition, and other fault models. Work on MBIST/LBIST integration and verification. Analyze test coverage and improve fault coverage metrics. Collaborate with design, verification, physical design, and validation teams for successful chip tape-out. Debug DFT-related issues during simulation and silicon bring-up. Ensure DFT deliverables meet quality, timing, and power requirements. Mandatory Skills Strong experience in: Scan Insertion & Scan Stitching ATPG Pattern Generation & Debug Scan Compression Techniques MBIST / LBIST JTAG / Boundary Scan DFT Verification Hands-on experience with tools such as: Tessent Synopsys DFT Compiler Tetramax / TestMAX Good understanding of: SoC Architecture RTL Design Concepts STA Basics Semiconductor fabrication and testing flow Strong debugging and problem-solving skills. Experience with Verilog/SystemVerilog scripting and Perl/TCL scripting is preferred. 

Preferred Qualifications: Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field. Experience in advanced technology nodes is an added advantage. Excellent communication and teamwork skills. 

Why Join Us? Opportunity to work on cutting-edge semiconductor technologies. Collaborative and innovation-driven work environment. Exposure to complex SoC programs and advanced DFT methodologies.