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We are looking for a skilled and motivated DFT Engineer with 5+ years of experience in VLSI design and verification. The ideal candidate should have strong expertise in Design for Testability (DFT) methodologies, scan insertion, ATPG, and d...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

Job Description: Portfolio & Governance Management • Support Project and portfolio planning, intake, prioritization, and execution reviews across programs and projects. • Prepare for monthly intake reviews, quarterly portfolio reviews, an...

PMO SAP Price2 Tools Data Quality & Automation

Completed graduation in Btech/Mtech from the background of EEE/ECE Good in concepts related to synthesis, place and route, CTS and timing convergence. Good knowledge and experience in Block-level Floor-planning and Physical verificati...

STA/Synthesis

We are looking for a SoC Verification Engineer responsible for verifying complex ASIC/SoC designs using SystemVerilog and UVM methodologies. The candidate will develop testbenches, create verification plans, debug RTL issues, and ensure fun...

SV UVM Debugging ARM SOC Verification

Key requirements include: • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis • Proficiency in simulation debug with timing/SDF • Experience with LBIST and Mixed Signal Radar ICs is highly desirable • Ability...

JTAG ATPG DRC LBIST

About the Role We are looking for a skilled and passionate Embedded Firmware Developer to join our engineering team in Noida. The ideal candidate will have hands-on experience in embedded systems development, microcontroller programming,...

Microcontroller: ARM Cortex-M STM32 NXP / LPC Microchip / PIC TI MSP430. Tool: STM32CubeIDE Keil IAR Embedded C C C++ (Embedded) Protocol: SPI I2C UART CAN USB Ethernet RS485 Modbus OS: FreeRTOS RTOS Bare metal Bootloader BSP

Job Summary We are looking for a skilled and motivated DFT (Design for Testability) Engineer with 3–5 years of experience in ASIC/SoC design and verification. The ideal candidate should have hands-on expertise in DFT implementation, scan i...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

ARM‑based System‑On‑Chip Pre‑Silicon emulation and Post‑Silicon Validation DDR (DDR3/DDR4/LPDDR4/LPDDR5) validation experience, including memory bring‑up, training, characterization and debug ASIC validation experience related to board br...

ARM C Language Trace32 DSP Processors

Job Description - Job responsibilities includes physical aware synthesis, STA, FV, constraint development & CLP activities. Hands-on experience with PD P & R and STA OR Synthesis along with Innovus tool as well will be suitable for these...

STA PnR Synthesis Innovus Fusion Compiler Primetime ICC1 ICC2

About the Role We are looking for a skilled and detail-oriented Analog Layout Engineer to join our VLSI design team in Bangalore. The ideal candidate will have strong expertise in custom analog/mixed-signal layout design and a deep underst...

Analog & Mixed Signal Layout Design Full Custom IC Layout Floorplanning & Routing Device Matching Techniques Common Centroid Layout Parasitic Extraction DRC LVS ERC Verification EM/IR Analysis Guard Ring & Shielding Techniques ESD Protection Concepts Cadence Virtuoso Calibre Assura/PVS CMOS Technology PLL Layout ADC/DAC Layout LDO Layout Bandgap Layout Tape-out Support