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Mandatory: Proficiency in RTL coding (VHDL/Verilog) for FPGA design. Strong understanding of Digital Signal Processing ( FFT/IFFT, Filter Design, Convolution, Cross Correlation, Auto-Correlation) concepts. Experience in Wireless Communicati...

RTL coding (VHDL/Verilog)  Digital Signal Processing ( FFT/IFFT Filter Design Convolution Cross Correlation Auto-Correlation) Wireless Communication protocols and algorithms

We are looking for an experienced Physical Verification Engineer with hands‑on experience in sign‑off verification of advanced technology nodes.The ideal candidate will be responsible for DRC, LVS, ERC, and physical sign‑off checks, working...

Physical verification sign‑off including DRC LVS ERC ANT and density checks

Job Description: We are looking for an experienced Formal Verification Engineer to join our team and work on advanced ASIC/SoC verification projects. The ideal candidate should have strong expertise in formal verification methodologies, ass...

Formal Verification SVA PSL Assertion-Based Verification JasperGold VC Formal Questa PropCheck RTL Verification ASIC Verification SoC Verification Equivalence Checking Property Checking Formal Coverage Analysis UVM Verilog SystemVerilog Debugging Coverage Closure

We are looking for a skilled Hardware Design Engineer with strong expertise in circuit design, PCB/board design, and board bring-up/debugging. The ideal candidate should be capable of reviewing customer schematics and layouts, identifying d...

Analog Circuit Design Digital Circuit Design PCB Design PCB Layout Review Board Bring-up Board Debugging Schematic Capture Schematic Review Layout Review Circuit Analysis Power Supply Design Signal Integrity Power Integrity High-Speed Interface Design Component Selection

Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-levelPreferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundriesExperience in developing sign-off methodolo...

LVS ERC/PERC DFM OPC Tape Out process Physical Verification calibre

Experience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)Prior work on Ethernet switching SoCs or Ethernet VIP developmentCreate detailed, specification-driven verification plans with clear feature d...

SV UVM ETHERNET

Job Title : Senior Physical Verification Engineer Experience : 5 to 10 Years Location : Bangalore Job Description :Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-levelPrefe...

Physical Verification DRC LVS Calibre PVS Assura

JD: DV EngineerExperience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)Prior work on Ethernet switching SoCs or Ethernet VIP developmentCreate detailed, specification-driven verification plans with...

SV UVM ETHERNET

Job Description: Portfolio & Governance Management • Support Project and portfolio planning, intake, prioritization, and execution reviews across programs and projects. • Prepare for monthly intake reviews, quarterly portfolio reviews, and...

PMO SAP Price2 Tools Data Quality & Automation

Completed graduation in Btech/Mtech from the background of EEE/ECE Good in concepts related to synthesis, place and route, CTS and timing convergence. Good knowledge and experience in Block-level Floor-planning and Physical verification. Wo...

STA/Synthesis