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Job Description: We are seeking a skilled and motivated Design Verification Engineer with 2-10 years of hands-on experience in verifying complex digital designs. You will be responsible for developing and executing verification strategies...

IP SOC C SystemVerilog UVM Verilog Coverage Assertions Constraints

experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on...

Calibre ICC2 Perl TCL

Must have experience in developing Verification environment from scratch Must be good in Verilog coding Must have Simulators experience using vcs/ncsim/modelsim Knowledge of UVM/VMM methodology is desirable

UVM/OVM Verilog

Should be expert in Verilog Coding Must have done Synthesis Must have worked on Scan insertion Should be familiar with Spyglass CDC/RDC Should be able to micro architect and code from specifications

CDC Spyglass Synthesis Verilog

Minimum of 3-4 years’ experience in ASIC/DFT – simulation and Silicon validation § Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement § In depth knowledge and hands-on experience in ATPG - covera...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

As a Silicon Validation Engineer , you will focus on carrying out post silicon validation for different IP blocks on leading edge process technology at IP/SOC level. Skilled use of standard lab equipment, including oscilloscopes, Logic ana...

1. Strong Verification skills with 7+ years of relevant experience 2. Proven Digital IP Verification expertise. 3. Proficient in SV, UVM 4. Knowledge of Ethernet MAC is added advantage 5. Strong communication skills

Ethernet MAC SV UVM

Job Description - Team should work on synthesis for complete DDRSS Subsystem (1 Subsystem (DL1) and 2 or 3 Blocks) and Hsc NoC Blocks. Number of blocks change from one project to another project. 1 person should be able to work on 2 cr...

CLP LEC Synthesis PD

Experience in ASIC/DFT – simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowl...

ATPG SCAN MBIST Simulation

5+Years of SoC verification experience Strong expertise in SystemVerilog, UVM, and assertions Experience with complex SoC architectures and standard protocols Strong debugging and problem-solving skills Familiarity with scripting and au...

SV UVM SOC C