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Silicon Validation EngineerAs a Silicon Validation Engineer, you will focus on carrying out post-silicon validation for different IP blocks on leading-edge process technologies at both IP and SoC levels.Skilled in the use of standard lab eq...

Strong verification skills with 7+ years of relevant experience.Proven expertise in Digital IP Verification.Proficient in SystemVerilog (SV) and UVM methodologies.Knowledge of Ethernet MAC is an added advantage.Strong communication and inte...

Ethernet MAC SV UVM

Job DescriptionThe team will work on synthesis for the complete DDRSS subsystem (1 subsystem - DL1 and 2 or 3 blocks) along with HSC NoC blocks.The number of blocks may vary from one project to another.One engineer should be capable of hand...

CLP LEC Synthesis PD

About the RoleWe are looking for a skilled and detail-oriented Analog Layout Engineer to join our VLSI design team in Bangalore. The ideal candidate will have strong expertise in custom analog/mixed-signal layout design and a deep understan...

Analog & Mixed Signal Layout Design Full Custom IC Layout Floorplanning & Routing Device Matching Techniques Common Centroid Layout Parasitic Extraction DRC LVS ERC Verification EM/IR Analysis Guard Ring & Shielding Techniques ESD Protection Concepts Cadence Virtuoso Calibre Assura/PVS CMOS Technology PLL Layout ADC/DAC Layout LDO Layout Bandgap Layout Tape-out Support

Experience in ASIC/DFT simulation and silicon validation.Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.In-depth knowledge and hands-on experience in ATPG and coverage analysis.Strong understand...

ATPG SCAN MBIST Simulation

Experience in EMIR analysis for multiple modes, including static and dynamic analysis with and without functional vectors.Strong expertise in understanding and debugging EMIR issues at the block level.Experience in power analysis for design...

Calibre ICC2 Perl TCL

Must have experience in developing verification environments from scratch.Strong proficiency in Verilog coding is required.Hands-on experience with simulators such as VCS, NCSim, and ModelSim.Knowledge of UVM/VMM verification methodologies...

UVM/OVM Verilog

Strong expertise in Verilog coding is required.Must have hands-on experience in synthesis.Experience with scan insertion is required.Familiarity with SpyGlass CDC/RDC tools is mandatory.Ability to perform micro-architecture development and...

CDC Spyglass Synthesis Verilog

We are looking for a trained fresher in Analog Layout / VLSI Layout who has a strong understanding of analog layout concepts and hands-on exposure to industry-standard layout tools.

Analog IC Layout fundamentals CMOS technology and VLSI concepts Transistor-level layout Understanding of schematics and circuit connectivity Layout vs. Schematic (LVS) Design Rule Check (DRC) Electrical Rule Check (ERC) Parasitic Extraction (PEX) Understanding of Design for Manufacturing (DFM)

✅ Knowledge of Scan, ATPG, MBIST, and DFT fundamentals✅ Passion for VLSI and semiconductor design✅ Freshers with relevant training are welcome

DFT DRC Scan compression EDT Logic BIST (LBIST) Memory BIST (MBIST) Test modes and test clocks Scan stitching ATPG pattern simulation Timing/no-timing simulation Basic understanding of PVT and timing constraints