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Minimum 3–4 years of experience in ASIC/DFT simulation and silicon validation.Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.In-depth knowledge and hands-on experience in ATPG and coverage analy...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

About the Role We are looking for a skilled and passionate Embedded Firmware Developer to join our engineering team in Noida. The ideal candidate will have hands-on experience in embedded systems development, microcontroller programming, re...

Microcontroller: ARM Cortex-M STM32 NXP / LPC Microchip / PIC TI MSP430. Tool: STM32CubeIDE Keil IAR Embedded C C C++ (Embedded) Protocol: SPI I2C UART CAN USB Ethernet RS485 Modbus OS: FreeRTOS RTOS Bare metal Bootloader BSP

Job SummaryWe are looking for a skilled and motivated DFT (Design for Testability) Engineer with 3–5 years of experience in ASIC/SoC design and verification.The ideal candidate should have hands-on expertise in DFT implementation, scan inse...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

Silicon Validation EngineerAs a Silicon Validation Engineer, you will focus on carrying out post-silicon validation for different IP blocks on leading-edge process technologies at both IP and SoC levels.Skilled in the use of standard lab eq...

Strong verification skills with 7+ years of relevant experience.Proven expertise in Digital IP Verification.Proficient in SystemVerilog (SV) and UVM methodologies.Knowledge of Ethernet MAC is an added advantage.Strong communication and inte...

Ethernet MAC SV UVM

Job DescriptionThe team will work on synthesis for the complete DDRSS subsystem (1 subsystem - DL1 and 2 or 3 blocks) along with HSC NoC blocks.The number of blocks may vary from one project to another.One engineer should be capable of hand...

CLP LEC Synthesis PD

About the RoleWe are looking for a skilled and detail-oriented Analog Layout Engineer to join our VLSI design team in Bangalore. The ideal candidate will have strong expertise in custom analog/mixed-signal layout design and a deep understan...

Analog & Mixed Signal Layout Design Full Custom IC Layout Floorplanning & Routing Device Matching Techniques Common Centroid Layout Parasitic Extraction DRC LVS ERC Verification EM/IR Analysis Guard Ring & Shielding Techniques ESD Protection Concepts Cadence Virtuoso Calibre Assura/PVS CMOS Technology PLL Layout ADC/DAC Layout LDO Layout Bandgap Layout Tape-out Support

Experience in ASIC/DFT simulation and silicon validation.Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.In-depth knowledge and hands-on experience in ATPG and coverage analysis.Strong understand...

ATPG SCAN MBIST Simulation

5+ years of experience in SoC verification.Strong expertise in SystemVerilog, UVM, and assertions.Experience working with complex SoC architectures and standard protocols.Strong debugging and problem-solving skills.Familiarity with scriptin...

SV UVM SOC C

Experience in EMIR analysis for multiple modes, including static and dynamic analysis with and without functional vectors.Strong expertise in understanding and debugging EMIR issues at the block level.Experience in power analysis for design...

Calibre ICC2 Perl TCL