Open Position
Synthesis Engineer
Semiconductor • Noida • 3 to 5 Years
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Posted 13 May 2026
Openings: 1
Last Apply: 13 May 2026
CLP
LEC
Synthesis
PD
Job Description
Job Description -
Team should work on synthesis for complete DDRSS Subsystem (1 Subsystem (DL1) and 2 or 3 Blocks) and Hsc NoC Blocks.
Number of blocks change from one project to another project.
1 person should be able to work on 2 critical blocks or 3 non-critical blocks on synthesis.
As part of synthesis, Following items to be taken care of
Timing convergence, Work with designers for design update if logic levels are high.
Work with PD team for floorplan update if floorplan is not proper.
Power (given by power team) & Area (design team) targets has to be met.
CLP should be made clean,
FV should be made clean,
Review the incoming collateral quality using a checklist and review all the items are clean before starting the synthesis.
Review the outgoing collaterals quality using a checklist.
Work with design team on porting the constraints from previous project to current project. Support the PD team on constraints updates that are required for the timing violations seen in PNR.
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Team should work on synthesis for complete DDRSS Subsystem (1 Subsystem (DL1) and 2 or 3 Blocks) and Hsc NoC Blocks.
Number of blocks change from one project to another project.
1 person should be able to work on 2 critical blocks or 3 non-critical blocks on synthesis.
As part of synthesis, Following items to be taken care of
Timing convergence, Work with designers for design update if logic levels are high.
Work with PD team for floorplan update if floorplan is not proper.
Power (given by power team) & Area (design team) targets has to be met.
CLP should be made clean,
FV should be made clean,
Review the incoming collateral quality using a checklist and review all the items are clean before starting the synthesis.
Review the outgoing collaterals quality using a checklist.
Work with design team on porting the constraints from previous project to current project. Support the PD team on constraints updates that are required for the timing violations seen in PNR.