Open Position
DFT Engineer
Semiconductor • chennai • 3-5 Years
Posted 14 May 2026
Openings: 3
Last Apply: N/A
DFT
Scan Insertion
ATPG
Scan Compression
MBIST
LBIST
JTAG
Boundary Scan
Verilog
SystemVerilog
ASIC/SoC Design
Flow Fault
Coverage Analysis
Tessent
Synopsys DFT Compiler
Tetramax/TestMAX
Cadence Modus
Debugging
Tcl/Perl/Python Scripting
Job Description
- Minimum 3–4 years of experience in ASIC/DFT simulation and silicon validation.
- Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG and coverage analysis.
- Strong knowledge of memory verification, repair, and failure root-cause analysis.
- Experience with any of the following tools is required:
- ATPG: TestKompress
- MBIST: Mentor ETVerify
- Simulation: VCS preferred, ModelSim
- Expertise in scripting languages such as Perl, Shell, etc. is an added advantage.
- Ability to work in an international team and dynamic environment with good communication skills.
- Ability to learn and adapt to new tools and methodologies.
- Ability to multitask and work on several high-priority designs in parallel.