DFT Engineer

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting

Minimum of 3-4 years’ experience in ASIC/DFT – simulation and Silicon validation
§ Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement
§ In depth knowledge and hands-on experience in ATPG - coverage analysis.
§ In depth knowledge of Memory verification, repair and failure root-cause analysis.
§ Experience with any of these tools is required
§ ATPG - TestKompress
§ MBIST - Mentor ETVerify
§ Simulation - VCS (preferred), modelsim.
§ Expertise in scripting languages such as Perl, shell, etc. is an added advantage
§ Ability to work in an international team, dynamic environment with good communication skills
§ Ability to learn and adapt to new tools, methodologies.
§ Ability to do multi-tasking & work on several high priority designs in parallel.