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Design Verification Engineer

Semiconductor • Bangalore • 4-8

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Posted 09 Jun 2026
Openings: 5
Last Apply: 22 Jun 2026
Ethernet. And strong in SV & UVM

Job Description

  • We are seeking a Design Verification Engineer with deep expertise in Ethernet protocols and advanced SystemVerilog (SV) and Universal Verification Methodology (UVM) techniques.You will own the verification lifecycle of high-speed Ethernet intellectual property (IP) and subsystem blocks, ensuring robust silicon functionality.
  •  
    1. Strong knowledge of Ethernet
    2. Experience in HVL such as SystemVerilog, UVM
    3. Experience in HDL such as Verilog
    4. Knowledge of ARM/DSP CPU architecture and high-speed peripherals like USB2/3, PCIE
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