Open Position
Memory Layout Design : Bangalore
Semiconductor • Bangalore • 3 to 5 Years , 5 to 8 Years
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Posted 04 Jun 2026
Openings: 1
Last Apply: 08 Jul 2026
Memory
Leafcell
DRC
LVS
Job Description
3-8 years of experience in Memory/Custom Layout design.
Memory Leafcell layout library design from scratch including top level integration.
Good knowledge on different types of memory architectures.
Good knowledge in optimized layout design for better performance.
Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow