Open Position
VERIFICATION ENGINEER
Semiconductor • Noida, Banglore • 3 – 5 YEARS
Posted 11 May 2026
Openings: 10
Last Apply: N/A
UVM/OVM
Verilog
Job Description
- Must have experience in developing verification environments from scratch.
- Strong proficiency in Verilog coding is required.
- Hands-on experience with simulators such as VCS, NCSim, and ModelSim.
- Knowledge of UVM/VMM verification methodologies is desirable.