Open Position
VERIFICATION ENGINEER
VERIFICATION • Noida, Banglore • 3 – 5 YEARS
Posted 11 May 2026
Openings: 10
Last Apply: N/A
UVM/OVM
Verilog
Job Description
Must have experience in developing Verification environment from scratch
Must be good in Verilog coding
Must have Simulators experience using vcs/ncsim/modelsim
Knowledge of UVM/VMM methodology is desirable
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Must be good in Verilog coding
Must have Simulators experience using vcs/ncsim/modelsim
Knowledge of UVM/VMM methodology is desirable