Open Position
RTL ENGINEER
Semiconductor • Noida • 3 – 5 YEARS
Posted 07 May 2026
Openings: 10
Last Apply: N/A
CDC
Spyglass
Synthesis
Verilog
Job Description
- Strong expertise in Verilog coding is required.
- Must have hands-on experience in synthesis.
- Experience with scan insertion is required.
- Familiarity with SpyGlass CDC/RDC tools is mandatory.
- Ability to perform micro-architecture development and coding based on design specifications.