Design Verification Engineer

IP SOC C SystemVerilog UVM Verilog Coverage Assertions Constraints

Job Description:
We are seeking a skilled and motivated Design Verification Engineer with 2-10 years of hands-on experience in verifying complex digital designs. You will be responsible for developing and executing verification strategies to ensure the functional correctness and robustness of our ASIC designs. This role offers the opportunity to work on cutting-edge technologies in a collaborative and fast-paced environment.

Develop and maintain UVM-based verification environments for block and system-level testing.
Create detailed test plans based on design specifications and architecture documents.
Write and execute directed and constrained-random test cases to achieve functional coverage goals.
Perform code and functional coverage analysis; identify and close coverage gaps.
Debug simulation failures using waveform viewers and log analysis tools.
Collaborate with RTL designers, architects, and software teams to resolve issues and improve design quality.
Contribute to regression setup, automation scripts, and continuous integration flows.
Document verification results and provide clear status updates to stakeholders.