Formal Verification Engineer : Remote

Formal Verification SVA PSL Assertion-Based Verification JasperGold VC Formal Questa PropCheck RTL Verification ASIC Verification SoC Verification Equivalence Checking Property Checking Formal Coverage Analysis UVM Verilog SystemVerilog Debugging Coverage Closure

Job Description: We are looking for an experienced Formal Verification Engineer to join our team and work on advanced ASIC/SoC verification projects. The ideal candidate should have strong expertise in formal verification methodologies, assertion-based verification, and debugging complex digital designs. Key Responsibilities: Develop and execute formal verification plans for complex ASIC/SoC designs Create and debug assertions using SystemVerilog Assertions (SVA) and PSL Perform property checking, equivalence checking, and formal coverage analysis Work closely with RTL designers to identify and resolve design issues early Debug formal failures and drive root cause analysis Contribute to verification methodology improvements and best practices Collaborate with cross-functional teams including design, DV, and architecture teams Required Skills: Formal Verification, SVA, PSL, Assertion-Based Verification, JasperGold, VC Formal, Questa PropCheck, RTL Verification, ASIC Verification, SoC Verification, Equivalence Checking, Property Checking, Formal Coverage Analysis, UVM, Verilog, SystemVerilog, Debugging, Coverage Closure Preferred Qualifications: Strong understanding of digital design fundamentals Experience in low-power verification, CDC/RDC verification is a plus Exposure to processor, interconnect, or protocol verification is an advantage Excellent debugging and problem-solving skills Why Join Us? 100% Remote Opportunity Work on cutting-edge semiconductor projects High-growth and collaborative work environment Exposure to advanced verification technologies