Physical Verification Engineer : Bangalore

Job Title : Senior Physical Verification Engineer 

Experience : 5 to 10 Years 

Location : Bangalore 

Job Description :

1. Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
2. Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
3. Experience in developing sign-off methodology/flow to and supporting a larger team
4. Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
5. Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
6. Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
7. Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)
8. Experience with ERC rules, PERC rules, ESD rules has an added advantage
9. Strong communication, problem-solving, and analytical skills