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We are looking for a trained fresher in Analog Layout / VLSI Layout who has a strong understanding of analog layout concepts and hands-on exposure to industry-standard layout tools.

Analog IC Layout fundamentals CMOS technology and VLSI concepts Transistor-level layout Understanding of schematics and circuit connectivity Layout vs. Schematic (LVS) Design Rule Check (DRC) Electrical Rule Check (ERC) Parasitic Extraction (PEX) Understanding of Design for Manufacturing (DFM)

✅ Knowledge of Scan, ATPG, MBIST, and DFT fundamentals✅ Passion for VLSI and semiconductor design✅ Freshers with relevant training are welcome

DFT DRC Scan compression EDT Logic BIST (LBIST) Memory BIST (MBIST) Test modes and test clocks Scan stitching ATPG pattern simulation Timing/no-timing simulation Basic understanding of PVT and timing constraints

Mandatory: Proficiency in RTL coding (VHDL/Verilog) for FPGA design. Strong understanding of Digital Signal Processing ( FFT/IFFT, Filter Design, Convolution, Cross Correlation, Auto-Correlation) concepts. Experience in Wireless Communicati...

RTL coding (VHDL/Verilog)  Digital Signal Processing ( FFT/IFFT Filter Design Convolution Cross Correlation Auto-Correlation) Wireless Communication protocols and algorithms

We are looking for an experienced Physical Verification Engineer with hands‑on experience in sign‑off verification of advanced technology nodes.The ideal candidate will be responsible for DRC, LVS, ERC, and physical sign‑off checks, working...

Physical verification sign‑off including DRC LVS ERC ANT and density checks

Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-levelPreferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundriesExperience in developing sign-off methodolo...

LVS ERC/PERC DFM OPC Tape Out process Physical Verification calibre

Experience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)Prior work on Ethernet switching SoCs or Ethernet VIP developmentCreate detailed, specification-driven verification plans with clear feature d...

SV UVM ETHERNET

JD: DV EngineerExperience in Ethernet protocols and standards (MAC interface – RGMII/RMII/MII, 802.3, 802.1Q etc)Prior work on Ethernet switching SoCs or Ethernet VIP developmentCreate detailed, specification-driven verification plans with...

SV UVM ETHERNET

Job Description: Portfolio & Governance Management • Support Project and portfolio planning, intake, prioritization, and execution reviews across programs and projects. • Prepare for monthly intake reviews, quarterly portfolio reviews, and...

PMO SAP Price2 Tools Data Quality & Automation

Completed graduation in Btech/Mtech from the background of EEE/ECE Good in concepts related to synthesis, place and route, CTS and timing convergence. Good knowledge and experience in Block-level Floor-planning and Physical verification. Wo...

STA/Synthesis

Minimum 3–4 years of experience in ASIC/DFT simulation and silicon validation.Detailed knowledge of DFT concepts, pattern simulation, silicon debug, and yield enhancement.In-depth knowledge and hands-on experience in ATPG and coverage analy...

DFT Scan Insertion ATPG Scan Compression MBIST LBIST JTAG Boundary Scan Verilog SystemVerilog ASIC/SoC Design Flow Fault Coverage Analysis Tessent Synopsys DFT Compiler Tetramax/TestMAX Cadence Modus Debugging Tcl/Perl/Python Scripting